Yield Simulation for Integrated Circuits


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The bubble 22 in FIG. The notch 44 is a result of reflection and scattering off of the defect towards the top of a nearby photoresist line This scattering also results in a significant lowering of the PAC concentration at the top of the line, which consequently gets developed away Other defects, besides bubbles 22, have been known to occur in the photoresist layer Because 0.

The impact of highly reflective 0. As a result, in the presence of particles 50, all photoresist 28 below the clear portion of the mask not shown may not get developed. As with the simulation results for photoresist bubbles 22 FIGS. As shown in FIG. As with the bubble 22 defects, the simulation also shows in phantom lines the nominal appearance of the photoresist lines 28 without any defect. The resulting defect profile from these simulations can also be stored and later used for comparison with actual wafer profiles. As with bubbles 22 in the photoresist 28, the impact of particles 50 is also position dependent.

In particular, the bridging 54 between lines 28 is more likely when the particle 50 is near the surface 14, and far from the substrate If the particle 50 is not centered in the exposed area, bridging 54 is less likely. The composition of the particle 50 also affects the resulting photoresist profile. The simulation results shown in FIG.

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If, on the other hand, the index of refraction of the material of the particle 50 is closer to that of photoresist 28, the effect is much less severe. Specifically, 0. If the index of refraction of the particle 50 is slightly above that of the photoresist 28, such as for nitride particles, only minor notching 56 of the photoresist profiles are observed.

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These effects can also be simulated see FIG. When the 0. For example, a bowl-like shape made entirely of photoresist 28 may occur surrounded by a circle of undeveloped photoresist. When the particle 70a is centered over an exposed area 72, it blocks the exposure FIG. On the other hand, if the particle 70c is centered over an unexposed area 74 FIG. The exposed area under the particle 70 is not caused by reflections off the substrate 20, which are in turn reflected off the lower surface of the particle Instead, light hitting the sides of the particle 70 is refracted and focused under the particle Particles made of other materials with similar refractive properties to photoresist 28, like oxide and nitride, will result in similar photoresist patterns.

The resulting photoresist profiles can also be used for comparison with actual wafer profiles, as described below. This defect pnenomenon is further illustrated by comparing simulation results of a tungsten particle with those of a photoresist particle. The tungsten particle results in widening of the photoresist line 28, but has no developed area under the particle 80 see FIG.

Turning now to FIG. Referring first to FIG.

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At step , in-line wafers are scanned and any defect data detected is stored for later comparison. The wafers are preferably scanned after predetermined process steps have been performed, as mentioned above. At step , a pareto of nominal wafer topography data is developed and stored for later comparison. At step , the most common defect types for the stored defect data are chosen.

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A process of elimination then begins where the chosen defect types are narrowed to identify the most likely cause of the observed defect. The elimination process begins by calibrating a simulator at step to match wafer topography for the nominal case. In the preferred embodiment, the Metropole simulator is used. At step , a plurality of defect simulations are executed by varying defect type, i. Location step a , size step b and composition step c of the defect are also varied as well.

The simulated defect profiles are then compared at step to the stored defect data. For each simulated defect profile, a comparison is made on whether it is a feasible or infeasible cause of the stored defective profile at step Experiments are then performed at step to narrow the range of feasible causes.

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Finally, at step a solution is identified for the most likely defect profile, and the defect is corrected according to this solution at step Referring now to FIG. The process begins at step where wafer electrical test "WET" data is reviewed. If a significant number of wafer sites have high resistance, and the distribution is non-uniform, then the failure analysis routine begins at step At step , a simulator is calibrated to match nominal WET data.

In the presently preferred embodiment, the Metropole simulator is used. Plural defect simulations are performed at step by varying particle types and implant types. Varying the position step a , size step b and composition step c of the defect are also simulated. The simulated electrical data are then compared at step to the measured WET results. The simulated defect profiles are classified at step as feasible or infeasible causes of the bad WET data. Tests are performed at step to narrow down the range of feasible causes.

Once a likely cause of the bad WET data is determined, a solution is identified at step , which is then implemented at step The invention provides a less costly and time consuming method for identifying various defects caused during the manufacture of IC wafers. Through the use of a defect simulation tool, such as the Metropole simulator, the impact of many different types of defects on photoresist profiles can be simulated and compared to in-line wafers. Defects such as bridging between photoresist lines caused by both very small bubbles and particles in the photoresist, as well as voids in the photoresist, caused by small bubbles or large particles on the photoresist surface, can be simulated and used for comparison to actual wafer defects.

The automation of the process of detecting causes for observed wafer defects presents a useful advance over prior experimental techniques known in the art. It is to be understood that a wide range of changes and modifications to the embodiments described above will be apparent to those skilled in the art and are contemplated. It is therefore intended that the foregoing detailed description be regarded as illustrative, rather than limiting, and that it be understood that it is the following claims, including all equivalents, that are intended to define the spirit and scope of the invention.

Effective date : Year of fee payment : 4. Year of fee payment : 8. Year of fee payment : Defects in integrated circuit wafers 10 are often difficult to diagnose, because patterned wafer inspections can only be done after certain wafer processing steps.

Defect simulation is used to understand the relation between defects in the wafer 10 and the resulting wafer profiles. Defects such as particles 50 and bubbles 22 in the photoresist 28 , for example, translate into a wide variety of defective profiles. Knowledge of the relation between defects and the defect profiles can assist in yield improvement efforts, since defects may be diagnosed by comparing simulated and observed defect profiles. From the simulated defect profiles, methods can be adapted to fix or correct observed defects. We claim: 1. A method of diagnosing defects that impact topography of an integrated circuit wafer surface, comprising the steps of: scanning an integrated circuit wafer surface after predetermined processing steps have been performed on the wafer;.

The method defined in claim 1, further comprising the step of fixing wafer surface defects according to known techniques based on the feasible defect causes identified. The method defined in claim 1, wherein the step of running predetermined experiments comprises the step of classifying defect types obtained from the predetermined experiments as feasible or infeasible causes of the defect profile.

The method defined in claim 1, wherein the step of running predetermined experiments comprises the step of running plural simulations of known defects. The method defined in claim 4, wherein the step of running plural simulations of known defects comprises varying both defect size and defect composition.

The method defined in claim 4, wherein the step of running plural simulations comprises the step of calibrating the simulator to match non-defective wafer topography. The method defined in claim 4, wherein the step of running plural simulations comprises the step of simulating the defects caused by unintended particles in wafer processing. The method defined in claim 4, wherein the step of running plural simulations comprises the step of simulating the defects caused by bubbles in wafer processing. The method defined in claim 4, wherein the step of running plural simulations comprises the step of simulating the defects caused by foreign material in wafer processing.

The method defined in claim 4, wherein the step of running plural simulations comprises the step of simulating the defects caused by chemical reactions in wafer processing. A method of developing a library of defects in integrated circuits, comprising the steps of: calibrating a defect simulator to match nominal wafer data for a non-defective integrated circuit;. The method defined in claim 11, wherein the step of running plural defect simulations comprises performing simulations for different exposure patterns. The method defined in claim 11, wherein the step of running plural defect simulations comprises the step of simulating the defects caused by unintended particles in wafer processing.

The method defined in claim 11 wherein the step of running plural defect simulations comprises the step of simulating the defects caused by bubbles in wafer processing. The method defined in claim 11 wherein the step of running plural defect simulations comprises the step of simulating the defects caused by foreign material in wafer processing.

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The method defined in claim 11, wherein the step of running plural defect simulations comprises the step of simulating the defects caused by chemical reactions in wafer processing. A method of detecting defects in integrated circuits that impact doping concentrations, comprising the steps of: measuring integrated circuit wafer electrical test data;. The method defined in claim 17, further comprising the step of fixing the identified defect according to known techniques.

The method defined in claim 17, wherein the bad wafer electrical test data comprises high resistance. The method defined in claim 17, wherein the bad wafer electrical test data comprises non-uniform distribution. The method defined in claim 17, wherein the bad wafer electrical test data comprises undesirable device performances. The method defined in claim 17, wherein the step of performing plural defect simulations comprises simulating particles blocking various types of wafer implants.


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The method defined in claim 17, wherein the step of performing plural defect simulations comprises simulating changes in defect position. The method defined in claim 17, wherein the step of performing plural defect simulations comprises simulating changes in defect size. The method defined in claim 17, wherein the step of performing plural defect simulations comprises simulating changes in defect composition.

A method for fixing defects in an integrated circuit wafer, comprising the steps of: simulating the effect caused by at least one known integrated circuit wafer defect;. USA en. Semiconductor device manufacturing system and method of manufacturing semiconductor devices.

Method and apparatus for updating a manufacturing model based upon fault data relating to processing of semiconductor wafers. Simulated defective wafer and pattern defect inspection recipe preparing method. Method and apparatus for detecting processing faults using scatterometry measurements. USB1 en. Method for prediction random defect yields of integrated circuits with accuracy and computation time controls.

Mask pattern of a semiconductor device and a method of manufacturing fine patterns using the same. Computer-aided manufacturing support method and system for specifying relationships and dependencies between process type components. USB2 en. Design structure and system for identification of defects on circuits or other arrayed products.

CNC en. JPB2 en. System and method for performing a mask verification using an individual mask error model. Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same. Low cost application of oxide test wafer for defect monitor in photolithography process.

CNB en. Xing, W. Bogaerts, T. Kaintura, D. Spina, I. Couckuyt, L. Knockaert, W. International Conferences U. Bogaerts, Parameter extraction, variability analysis and yield prediction of the photonic integrated circuits. Ye, U. Khan, J. Dong, J. Geessels, M. Fiers, D. Spina, T.

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Xing, M. Wang, A. Ruocco, J. Geessels, U. Xing, A. Ribeiro, W. Dong, U. Dhaene, W. Bogaerts, U.

Yield Simulation for Integrated Circuits Yield Simulation for Integrated Circuits
Yield Simulation for Integrated Circuits Yield Simulation for Integrated Circuits
Yield Simulation for Integrated Circuits Yield Simulation for Integrated Circuits
Yield Simulation for Integrated Circuits Yield Simulation for Integrated Circuits
Yield Simulation for Integrated Circuits Yield Simulation for Integrated Circuits
Yield Simulation for Integrated Circuits Yield Simulation for Integrated Circuits
Yield Simulation for Integrated Circuits Yield Simulation for Integrated Circuits
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